High-resolution, high-precision solid-state potentiometer

ABSTRACT

Disclosed are solid-state potentiometers having high resolution and high accuracy. An exemplary potentiometer comprises a first main terminal, a second main terminal, a wiper terminal, and a resistor stack comprising a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes. Each of the resistors in the stack has substantially the same value of R S  ohms. The potentiometer further comprises a first variable resistance network coupled between one end of the resistor stack and the potentiometer&#39;s first main terminal, and a second variable resistance network coupled between the other end of the resistor stack and the potentiometer&#39;s second main terminal. The first variable resistance network has a variable resistance value R 1  which varies between zero ohms and R P  ohms. The second variable resistance network has a variable resistance value R 2  which is maintained substantially at value of (R P −R 1 ). The wiper terminal is selectively coupled to one of the internal nodes of the resistor stack, or to one of the ends of the resistor stack, to provide a coarse setting of the potentiometer&#39;s wiper position. The resistances of the variable resistance networks are changed to provide the fine resolution for the potentiometer&#39;s wiper position. The present invention provides a large number of discrete wiper positions with a constant end-to-end resistance, while using a small number of resistors and transistors relative to prior art implementations. A further advantage of the invention is that the potentiometer may be constructed with a small number of selection transistors turned on within the current path between the potentiometer&#39;s main terminals, thereby providing higher accuracy.

FIELD OF THE INVENTION

[0001] The present invention relates generally to the field of variable impedance elements and more specifically to solid-state variable impedance elements for use in electronic circuits.

BACKGROUND OF THE INVENTION

[0002] Electronic circuits containing variable impedance elements are well known to the art. These variable impedance elements are usually in the form of variable resistors, also called potentiometers. Circuits using variable inductors or capacitors are also well known. These variable impedance elements are usually manually adjusted to provide a selected impedance so as to affect some aspect of the circuit in which they are located. For example, a potentiometer may be set to a value which maximizes a signal generated at a node in a given circuit.

[0003] Manual adjustment of potentiometers is usually unsatisfactory in circuits under the control of data processing systems or other external electric circuits where ongoing adjustment of the potentiometer is necessary for circuit operation. The data processing system often must change the value of the variable impedance element in a time that is short relative to the time required to complete a manual adjustment of the variable impedance element. Manual adjustment also requires the presence of a human operator which is impractical in many situations in which variable impedance elements are employed. Remote control of resistance by a computer or digital system is needed in many applications.

[0004] Potentiometers which are adjusted mechanically by motors or other actuators under external control are also known to the prior art. Although these potentiometers relieve the need for an operator, they are still unsatisfactory in many applications. First, the time to make an adjustment is still too long for many applications. Second, the long term reliability of such electromechanical devices is not sufficient for many applications requiring variable impedance elements. Finally, such systems are often too large and economically unattractive for many applications.

[0005] Solid-state potentiometers have been developed as a solution to the above problems. These potentiometers generally comprise a network of resistors that are selectively connected to a wiper terminal by a network of transistors, all of which are integrated onto a single chip of semiconductor. Because fixed-values resistors are used and because the wiper position is selected by one or more transistors, the resistance value between a wiper and a main terminal of a solid-state potentiometer can only have a finite number of values. As an example, a 16-value solid-state potentiometer may comprise 15 equal-value resistors connected in series to form a series resistor stack, with the stack being connected between the two main terminals of the potentiometer. A select transistor is then coupled between each internal node of the series-resistor stack and the wiper terminal, and between each main terminal and the wiper terminal, for a total of 16 select transistors. One of the select transistors is set in a conducting state to select one point along the series-resistor stack. As can be seen by this example, the number of resistors and transistors required to implement a solid-state potentiometer increases linearly with the desired number of discrete values. In general, the chip area and cost of implementing a solid-state potentiometer increase, and the number of resistors and transistors increase, as the number of discrete values increases.

[0006] Since the development of solid-state potentiometers, there has been a desire to find a combination of resistors and transistors that provides a larger number of discrete values with less chip area.

SUMMARY OF THE INVENTION

[0007] The present invention encompasses solid-state potentiometers that can provide a large number of discrete values using a small number of components, and therefore requiring less chip area and less cost to manufacture.

[0008] Broadly stated, a potentiometer according to the present invention comprises a first main terminal, a second main terminal, a wiper terminal, and a resistor stack comprising a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes, each internal node coupling two adjacent resistors of the stack. Each of the resistors in the stack has substantially the same value of R_(S) ohms, each of the resistors preferably being within 0.1·R_(S) of R_(S). The potentiometer further comprises a first variable resistance network coupled at one end of the resistor stack and a second variable resistance network coupled at the other end of the resistor stack. The first variable resistance network has a first terminal coupled to the potentiometer's first main terminal, a second terminal coupled to the free terminal of the first resistor in the resistor stack, and a variable resistance value R₁ which varies between zero ohms and R_(P) ohms. R_(P) has a value of between 0.75·R_(S) and 1.25·R_(S), and preferably between 0.75·R_(S) and R_(S).

[0009] The second variable resistance network has a first terminal coupled to the potentiometer's second main terminal, a second terminal coupled to the free terminal of the last resistor in the resistor stack, and a variable resistance value R₂ which is maintained substantially at value of (R_(P)−R₁). The wiper terminal is selectively coupled to one of the internal nodes of the resistor stack, or to one of the second terminals of the variable resistor networks, to provide a coarse setting of the potentiometer. (The wiper terminal may also be selectively coupled to either of the potentiometer's main terminals in order to provide a “rail-to-rail” range for the potentiometer.) The resistances of the variable resistance networks are changed to provide the fine resolution for the potentiometer.

[0010] As indicated above, in preferred embodiments, the resistance R₂ of the second variable resistance network is coordinated in a complementary manner (R₂≈R_(P)−R₁) to the resistance R₁ of the first variable resistance network so that the sum of these two resistances is approximately constant (R₁+R₂=R_(P)) for any wiper setting of the potentiometer. By approximately constant, we mean that the sum R₁+R₂ is at least within 10% of R_(P). This results is the resistance between the main terminals of the potentiometer being kept at a substantially constant value (i.e., maintaining a constant end-to-end resistance). This is a tremendous improvement over R−2R ladder networks, which have widely varying end-to-end resistances. In addition, the value of R_(P) is selected to be near to the value of resistance R_(S) of each resistor in the resistor stack. In preferred linear potentiometer embodiments, each variable resistance network has a plurality N of resistance values which are spaced substantially equally from one another by an increment ΔR_(P) as follows: 0, ΔR_(P), 2·ΔR_(P), 3·ΔR_(P), . . . , (N−1)·ΔR_(P). In addition, the value of R_(P) is substantially equal to the quantity (R_(S)−ΔR_(P)), preferably being within ½·ΔR_(P), of that quantity, and more preferably within ¼·ΔR_(P), and most preferably within 0.1·ΔR_(P). With N discrete resistance values in the variable resistance networks, and M resistors in the resistor stack, a linear embodiment of the potentiometer will have (M+1)·N discrete values.

[0011] In a preferred embodiments of the present invention, each variable resistor network comprises a parallel combination of resistors which are selectively turned on and off by respective switches (e.g., transistors) to provide a range of discrete steps between 0 ohms and R_(P) ohms. In linear potentiometers, these steps are substantially equal.

[0012] The above combination of two coordinated variable resistance networks placed on either side of a resistor stack enables one to construct a solid-state potentiometer which provides a large number of discrete wiper positions (values) with a constant end-to-end resistance, while using a small number of resistors and transistors relative to prior art implementations. A further advantage of the invention is that the potentiometer may be constructed with a small number of selection transistors turned on within the current path between the potentiometer's main terminals, thereby providing higher accuracy.

[0013] Accordingly, it is an object of the present invention to provide a topology for a digitally control potentiometer which enables the construction of a solid-state potentiometer which has a larger number of discrete values while using less chip area and fewer transistors relative to prior art implementations.

[0014] It is another object of the present invention to minimize the number of selection transistors in the main current path between the main terminals of the potentiometer in order to increase the accuracy of the potentiometer.

[0015] It is yet another object of the present invention to provide a topology for a digitally controlled potentiometer which enables the construction of a solid-state potentiometer which has a larger number of discrete values while achieving a constant end-to-end resistance.

[0016] These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention, the accompanying drawings, and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a schematic diagram of a first potentiometer embodiment according to the present invention.

[0018]FIG. 2 is a schematic diagram of a second potentiometer embodiment according to the present invention.

[0019]FIG. 3 shows an exemplary implementation of a switch used in the potentiometer shown in FIG. 2 according to the present invention.

[0020]FIG. 4 shows an exemplary control circuit for activating selection transistors for the embodiment of FIG. 2 according to the present invention.

[0021]FIG. 5 shows another implementation of the first variable resistor network according to the present invention.

[0022]FIG. 6 shows another implementation of the second variable resistor network according to the present invention.

[0023]FIG. 7 shows another implementation of the second variable resistor network according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0024]FIG. 1 shows a schematic diagram of a first potentiometer embodiment 10 according to the present invention. Potentiometer 10 comprises a first main terminal 11, a second main terminal 12, and a wiper terminal 13. In general applications of potentiometer 10, a voltage is applied between main terminals 11 and 12 by applying voltages V_(H) and V_(L) respectively to these terminals, with an intermediate potential V_(W) being tapped off by the wiper terminal 13.

[0025] Potentiometer 10 further comprises a first variable resistance network 20 which has a first terminal 21 coupled to main terminal 11, a second terminal 22, and a variable resistance value R₁ which varies between zero ohms and a value of R_(P) ohms. Potentiometer 10 further comprises a second variable resistance network 40 which has a first terminal 41 coupled to main terminal 12, a second terminal 42, and a variable resistance value R₂ which varies between zero ohms and R_(P) ohms. In addition, resistance R₂ is set substantially at a value of (R_(P)−R₁), which is complementary to the value of the first variable resistance network.

[0026] In addition, potentiometer 10 comprises a resistor stack 60 having a plurality M of resistors 62 ₁, 62 ₂, 62 ₃, . . . , 62 _(M−1), 62 _(M) coupled in series to one another at a plurality of M−1 internal nodes 64 ₁, 64 ₂, . . . , 64 _(M−2), 64 _(M−1), each internal node 64 _(k) coupling two adjacent resistors 62 _(k) and 62 _(k+1) of the stack, as shown in the figure. The top resistor 62 _(M) of stack 60 has its free terminal (the one not coupled to internal node 64 _(M−1)) coupled to second terminal 22 of first variable resistance network 20. Similarly, the bottom resistor 62 ₁ of stack 60 has its free terminal (the one not coupled to internal node 64 ₁) coupled to second terminal 42 of second variable resistance network 40. In preferred linear potentiometer embodiments of the present invention, each of resistors 62 _(k) has a value substantially equal to a value of R_(S) ohms, preferably being with 10% or less of R_(S).

[0027] Potentiometer 10 also comprises a selector 80 which selects one of the internal nodes 64 _(k) or the second terminals 22 and 42 of the variable resistor networks, and couples the selected node or terminal to wiper terminal 13. In preferred embodiments, selector 80 also selects from the potentiometer's main terminals 11 and 12 in order to provide a full “rail-to-rail” range for the wiper. Selector circuit 80 provides a coarse setting of the potentiometer, while variable resistor networks 20 and 40 provide a fine resolution between each coarse setting of selector 80. For example, to change wiper 13 from a low potential V_(L) at second main terminal 12 through all of the available potentiometer values to a high potential V_(H) at first main terminal 11, one would execute the following steps:

[0028] 1. first set selector 80 to the “Bottom” switch position;

[0029] 2. then move selector 80 to the “0” switch position with R₂ set to zero and R₁ set to R_(P);

[0030] 3. then increase R₂ in value by discrete steps (while decreasing R₁ in a complementary manner) until R₂ reaches R_(P);

[0031] 4. then increment selector 80 to the next position with R₂ set to zero and R₁ set to R_(P); and

[0032] 5. then repeat steps 3 and 4 until selector 80 is incremented to the “Top” position.

[0033] In preferred linear potentiometer embodiments, each of variable resistance networks 20 and 40 has a plurality N of resistance values which are spaced substantially equally from one another by an increment ΔR_(P) as follows: 0, ΔR_(P), 2·ΔR_(P), 3·ΔR_(P), (N−1)·ΔR_(P), with ΔR_(P)=R_(P)/(N−1), with each resistance value being within ½·ΔR_(P) of its target value, and preferably within ¼·ΔR_(P) of its target value, and most preferably within 0.1·ΔR_(P) of its target value. In addition, the value of R_(P) is substantially equal to the quantity (R_(S)−ΔR_(P)), preferably being within ½·ΔR_(P), of that quantity, and more preferably within ¼·ΔR_(P), or less. With N discrete resistance values in variable resistance networks 20 and 40, and with M resistors in the resistor stack, a linear embodiment of the potentiometer will have (M+1)·N possible discrete position values for its wiper. To provide reasonable linearity of the potentiometer, each of the resistors 63 _(K) in resistor stack 60 has a value that is within ½·ΔR_(P) of R_(S); to provide better linearity, each resistor 63 _(K) has a value that is within ¼·ΔR_(P) of R_(S); in preferred embodiments, each resistor 63 _(K) has a value that is within 0.1·ΔR_(P) of R_(S). In addition, the sum of the resistances R₁+R₂ is at least within 10% of R_(P), and preferably within ½·ΔR_(P) of R_(S).

[0034]FIG. 2 shows a schematic diagram of a second embodiment 100 of a potentiometer according to the present invention. Potentiometer 100 comprises first main terminal 11, second main terminal 12, wiper terminal 13, and resistor stack 60 as previously described, and comprises a first variable resistance network 120, a second variable resistance network 140, and a selector 180 in place of network 20, network 40, and selector 80, respectively, of FIG. 1. Each of networks 120 and 140 have the functions and properties of their counterparts 20 and 40, respectively, and are specific implementations thereof. Likewise, selector 180 has the functions and properties of its counterpart selector 80, and is a specific implementation thereof.

[0035] Variable Resistance Network 140

[0036] We will describe second variable resistance network 140 first. Variable resistance network 140 comprises a first terminal 141 coupled to second main terminal 12, a second terminal 142A coupled to the bottom resistor of resistor stack 60, a sense terminal 142B coupled to selector 180, and a plurality N of parallel current branches, each branch being coupled between the first terminal 141 and the second terminal 142A. The first current branch comprises a switch 146 ₀ coupled between terminals 141 and 142A, and provides an infinite resistance when switch 146 ₀ is open, and near zero resistance (R_(ON) in practice, as described below) when the switch is closed. The remaining N−1 current branches comprise a plurality of resistors 144 ₁ through 144 _(N−1) and a corresponding plurality of double-pole, single-throw switches 146 ₁ through 146 _(N−1) Each one of these branches comprises one of the resistors 144 _(K) (K=1 through K=N−1) coupled in series with the first pole of one of the corresponding switches 146 _(K), with the series combination being coupled between terminals 141 and 142A, as shown in FIG. 2. Each resistor 144 _(K) (K=1 through K=N−1) is also coupled to the second pole of its corresponding switch 146 _(K), with this series combination being coupled between terminals 141 and 142B. This arrangement of two-poles per switch 146 _(K), with the first pole coupled to resistor stack 60 through second terminal 142A and the second pole coupled to selector 180 through sense terminal 142B, enables selector 180 to measure the voltage across the corresponding resistor 144 _(K) directly without having to measure the voltage drop that may be developed across switch ¹⁴⁶ _(K). In this manner, sense terminal 142B acts as an “ideal” second terminal of network 140 for selector 180.

[0037] It is noted that switch 146 ₀ does not use a second pole like the other switches 146 _(K); this is because, as described below in greater detail, selector 180 does not couple to sense terminal 142B through switch 182 ₀ when switch 146 ₀ is conducting, which would normally occur when the wiper is set to the lower rail at voltage V_(L). Instead, under this condition, selector 180 selects the rail voltage V_(L) through switch 182 _(BOT), obviating the need for the sensing performed by sense terminal 142B and the second poles of the switches. Nonetheless, in other applications, or in applications where switch 182 _(BOT) is not used, switch 146 ₀ may be augmented to include a second pole coupled between first terminal 141 and sense terminal 142B.

[0038] Network 140 provides a plurality N of resistance values which are spaced substantially equally from one another by an increment ΔR_(P) as follows: 0, ΔR_(P), 2·ΔR_(P), 3·ΔR_(P), . . . , (N−1)·ΔR_(P). This is accomplished by setting the value of resistors 144 ₁ through 144 _(N−1) substantially equal to the values ΔR_(P), 2·ΔR_(P), 3·ΔR_(P), . . . , (N−1)·ΔR_(P), as shown in the figure, and by closing only one of switches 146 while leaving the other switches in open positions. By “substantially equally” and “substantially equal”, we mean each resistance value and each resistor value is at least within ½·ΔR_(P) of its target value, and preferably within ¼·ΔR_(P) of its target value. In practice, each of switches 146 ₀−146 _(N−1) is implemented by two or more transistors. A preferred implementation of switch 146 is shown in FIG. 3, which shows two conventional analog CMOS switches, one for each pole. Each CMOS switch comprises an NMOS transistor and a PMOS transistor coupled with their conduction terminals in parallel, and being driven by complementary logic signals at their gates. Referring back to FIG. 2, each switch 146 ₀−146 _(N−1) may only comprise a single NMOS transistor for each of its poles (one NMOS transistor per pole) if the following condition will exist in the specific application for potentiometer 100: the voltage V_(L) will always be much less than V_(ON,N)−V_(TH,N), where V_(ON,N) is the voltage applied to the gate of the NMOS transistor to set it in its conducting state, and where V_(TH,N) is the threshold voltage of the NMOS transistor.

[0039] In practice, the transistor(s) of each switch 146 have a collective finite resistance RON when they are in their conducting state(s). If RON is ten percent or more of the value of ΔR_(P), then corrective measures may need to be taken to improve the accuracy of the potentiometer. A first corrective action, as alluded to above, is to provide a second pole with each switch 146 ₁−146 _(N−1), with the second pole coupled between sense terminal 142B (and thereby selector 180) and the corresponding resistor 144 ₁−144 _(N−1). Assuming that very little current flows from the wiper terminal 13, then the voltage drop across the second pole is virtually zero when the switch is closed. In contrast, the first pole of the switch, which is coupled to resistor stack 60, will be carrying the current between main terminals 11 and 12 when the switch is closed, and a voltage drop will be developed. A second corrective action is to determine the average value of RON for the application that is anticipated for potentiometer 100, and to then subtract this amount from the resistance values of each of resistors 144 ₁−144 _(N−1). In this case, then second poles of the switches 146 ₁−146 _(N−1), can be omitted, and selector 180 may be coupled to terminal 142A.

[0040] Variable Resistance Network 120

[0041] Similar to network 140, first variable resistance network 120 comprises a first terminal 121 coupled to first main terminal 11, a second terminal 122A coupled to the top resistor of resistor stack 60, a sense terminal 122B coupled to selector 180, and a plurality of N parallel current branches. The first N−1 current branches comprise a plurality of resistors 124 ₀ through 124 _(N−2) and a corresponding plurality of double-pole, single-throw switches 126 ₀ through 126 _(N−2). Each one of these branches comprises one of the resistors 124 _(K) (K=0 through N−2) coupled in series with the first pole of one of the corresponding switches 126 _(K), with the series combination being coupled between terminals 121 and 122A, as shown in FIG. 2. Each resistor 124 _(K) (K=1 through N−2) is also coupled to the second pole of its corresponding switch 126 _(K), with this series combination being coupled between terminals 121 and 122B. This arrangement of two-poles per switch 126 _(K), with the first pole going to resistor stack 60 and the second pole going to selector 180, enables selector 180 to measure the voltage across the corresponding resistor 124 _(K) directly without having to measure the voltage drop that may be developed across switch 126 _(K), as previously described above. In this manner, sense terminal 122B acts as an “ideal” second terminal of network 120 for selector 180. The last current branch comprises a switch 126 _(N−1) coupled between terminals 121 and 122A, and provides an infinite resistance when switch 126 _(N−1) is open, and near zero resistance (R_(ON) in practice) when the switch is closed. Like switch 146 ₀ of network 140, switch 126 _(N−1) need not have a second pole for the reason that selector 180 will select the top rail voltage V_(H) through switch 182 _(TOP); however, in other applications a second pole may be added to switch 126 _(N−1) Network 120 provides a plurality N of resistance values which are spaced substantially equally from one another by an increment ΔR_(P) as follows: (N−1)·ΔR_(P), (N−2)·ΔR_(P) . . . , 3·ΔR_(P), 2·ΔR_(P), ΔR_(P), and 0. This is accomplished by setting the value of resistors 124 ₀ through 124 _(N−2) substantially equal to the values (N−1)·ΔR_(P), (N−2)·ΔR_(P), . . . , 3·ΔR_(P), 2·ΔR_(P), and ΔR_(P), as shown in the figure, and by closing only one of switches 126 while leaving the other switches in open positions. By “substantially equally” and “substantially equal”, we mean each resistance value and each resistor value is at least within ½·ΔR_(P) of its target value, and preferably within ¼ΔR_(P) of its target value. These resistances are arranged in descending order, while the resistors 146 of network 140 are arranged in ascending order. In the operation of potentiometer 100, the K-th switch 126 _(K), K=0 to N−1, is closed when the corresponding K-th switch 146 _(K), of network 140 is closed. This results in the sum of resistors activated by switches 126 _(K) and 146 _(K) always being equal to (N−1)·ΔR_(P)=R_(P).

[0042] In practice, each of switches 126 ₀−126 _(N−1) is implemented by two or more transistors. A preferred implementation of transistor 126 is shown in FIG. 3, as previously described. Each switch 126 ₀−126 _(N−1) may only comprise a single PMOS transistor for each of its poles (one PMOS transistor per pole) if the following condition will exist in the specific application for potentiometer 100: the voltage V_(H) will always be much greater than V_(ON,P)+V_(TH,P), where V_(ON,P) is the voltage applied to the gate of the PMOS transistor to set it in its conducting state, and where V_(TH,P) is the threshold voltage of the PMOS transistor. The same corrective actions described above for accounting for the conducting resistance RON of the switches 146 may be taken for switches 126.

[0043] Selector 180

[0044] Selector 180 is relatively simple. It comprises a first switch 182 _(BOT) coupled between second main terminal 12 and wiper terminal 13, a second switch 182 ₀ coupled between the sense terminal 142B of second variable resistance network 140 and wiper terminal 13, a third switch 182 _(M) coupled between the sense terminal 122B of first variable resistance network 120 and wiper terminal 13, and a fourth switch 182 _(TOP) coupled between first main terminal 11 and wiper terminal 13. Selector 180 further comprises a plurality of M−1 additional switches 182 ₁ through 182 _(M−1), each of which is coupled between a corresponding internal node 64 _(k) of resistor stack 60 and wiper terminal 13, as shown in FIG. 2. Each of switches 182 _(BOT), 182 _(TOP), and 182 ₀−182 _(M) preferably comprises a single CMOS transistor switch, as shown in FIG. 3.

[0045] Switch Selector Circuit

[0046] In general, it will be convenient for a user to specify the wiper position of the potentiometer with a single y-bit digital number. A circuit may then be used to receive this number, and generate signals to transistors 126, 146, and 182 which implement the specified wiper position. FIG. 4 provides an exemplary circuit 400 for the case where a 6-bit digital number is supplied (y=6). The three least significant bits will be used to select from 8 different values in each of the variable resistance networks 120 and 140, and the three most significant bits will be used to select from the six internal nodes that are between 7 resistors of resistor stack 60 and the two second terminals of networks 120 and 140. The bits of the number are received and latched in by latches 401 and 402, which latch the 3 least-significant bits and 3 most-significant bits respectively. The outputs of latches 401 and 402 are directed to respective 3-to-8 de-multiplexers 411 and 412, respectively. The outputs of de-multiplexer 411 generates the control signals to transistors 126 and 146 of variable networks 120 and 140, as shown in the figure.

[0047] Switch 182 _(BOT) is to be set in a conducting state when the input digital word is equal to zero. A signal for this switch may be readily generated by logically ANDing together the “0” -line outputs of de-multiplexers 411 and 412, as is done by AND gate 421. When the input digital words has values of 1 (000001) through 7 (000111), switch 182 ₀ is to be set in a conducting state. A signal for this can be generated by ANDing together the complement of the “0” -line output of de-multiplexer 411 with the “0” -line output of de-multiplexer and 412, as is done by inverter 422 and AND gate 423. The control signals for switches 182 ₁ through 182 ₆ are provided by the “1”-line output through the “6” -line output, respectively, of de-multiplexer 412. Switch 182 _(TOP) is to be set in a conducting state when the input digital number has a value of 2⁶−1 (111111). A signal for this switch may be readily generated by logically ANDing together the “7” -line outputs of de-multiplexers 411 and 412, as is done by AND gate 425. Finally, when the input digital words has values of 2⁶−8 (111000) through 2⁶−2 (111110), switch 182 _(M) is to be set in a conducting state. A signal for this can generated by ANDing together the complement of the “7” -line output of de-multiplexer 411 with the “7” -line output of de-multiplexer and 412, as is done by inverter 426 and AND gate 427.

[0048] The circuitry described above only allows one of transistors 182 to be on at a time.

[0049] Additional Embodiments of the Variable Resistance Networks

[0050] It may be appreciated that each of variable resistance networks 20 and 40 may be implemented with a line of series-connected resistors rather than parallel configured resistors. As an example, FIG. 5 shows a variable network 520 comprising a line of N−1 series-connected resistors 124 ₀ through 124 _(N−2), each with a value substantially equal to ΔR_(P), and N double-pole selection switches 126 ₀ through ¹²⁶ _(N−1) The first and last resistors each having a free terminal which is not connected to an intermediate node, each free terminal being an end of the resistor line. One end of the line of series-connected resistors is coupled to first terminal 121. The first pole of each switch 126 is coupled to second terminal 122A, and the second pole of each switch 126 (except for switch 126 _(N−1)) is coupled to sense terminal 122B. Each resistor 124 _(K) has a value that is within ½·ΔR_(P) of ΔR_(P), and preferably within ¼·ΔR_(P) of ΔR_(P), and more preferably 0.1·ΔR_(P) of ΔR_(P).

[0051]FIG. 6 shows the corresponding embodiment 540 for second resistor network 140. It is a mirror image of embodiment 520 taken along a horizontal line above embodiment 540.

[0052] It may be appreciated that, instead of using sense terminals 122B and 142B, networks 520 and 540 may be compensated for the average on-resistance R_(ON) of the switches. For the topology of network 520, the average value of R_(ON) is subtracted from the resistance values of only resistor 124 _(N−2). For the topology of network 540, the average value of R_(ON) is subtracted from the resistance values of only resistor 144 ₁.

[0053] Another embodiment of the second variable resistor network is shown at 740 in FIG. 7, which provides 12 resistance values, and optionally 16 resistance values. Network 740 comprises a first parallel network 710 coupled in series with a second parallel network 720 at an intermediate node 705, with the series combination coupled between first and second terminals 141 and 142A. First parallel network 710 comprises three current branches that are coupled between node 705 and first terminal 141: the first branch comprises a switch 711, the second branch comprises a switch 712 coupled in series with a resistor having a value of ΔR_(P), and the third branch comprises a switch 713 coupled in series with a resistor having a value of 8·ΔR_(P). Second parallel network 720 comprises five current branches (and optionally a sixth one as shown in dashed lines), each branch being coupled between intermediate node 705 and the second terminal 142A. The first current branch comprises a switch 721 coupled between intermediate node 705 and terminal 141, and provides an infinite resistance when switch 721 is open, and near zero resistance when the switch is closed. The remaining four (or five) current branches comprise a plurality of double-pole, single-throw switches 722-725 (and optionally switch 726), each having its first pole coupled in series with a respective resistor, with the series combination being coupled between intermediate node 705 and terminal 142A. Switch 722 is coupled in series with a resistor having a value of 3·ΔR_(P), switch 723 is coupled in series with a resistor having a value of 6·ΔR_(P), switch 724 is coupled in series with a resistor having a value of 9·ΔR_(P), switch 725 is coupled in series with a resistor having a value of 12·ΔR_(P), and optional switch 726 is coupled in series with a resistor having a value of 15·ΔR_(P). Each of these resistors is also coupled to the second pole of its corresponding switch 722-725 (and optionally 726), with this series combination being coupled between intermediate node 705 and terminal 142B for the sensing operation, as previously described above. Twelve different values of resistance are provided by network 740 by closing the following switches, and indicated in TABLE I: TABLE I  0 Switches 721 and 711  ΔRp Switches 721 and 712  2 · ΔRp Switches 722, 723, and 711  3 · ΔRp Switches 722 and 711  4 · ΔRp Switches 723, 725, and 711  5 · ΔRp Switches 723, 725, and 712  6 · ΔRp Switches 723 and 711  7 · ΔRp Switches 723 and 712  8 · ΔRp Switches 721 and 713  9 · ΔRp Switches 724 and 711 10 · ΔRp Switches 724 and 712 11 · ΔRp Switches 722 and 713

[0054] By including a sixth branch formed by switch 726 and a resistor having a value of 15·ΔR_(P), four more steps may be added for a total of 16, as indicated in Table II: TABLE II 12 · ΔRp Switches 725 and 711 13 · ΔRp Switches 725 and 712 14 · ΔRp Switches 723 and 713 15 · ΔRp Switches 726 and 711

[0055] The same set of values may be obtained by changing the value of the resistor connected in series with switch 713 of the first parallel network to 2·ΔR_(P), and using the following selection of switches: TABLE III  0 Switches 721 and 711  ΔRp Switches 721 and 712  2 · ΔRp Switches 721 and 713  3 · ΔRp Switches 722 and 711  4 · ΔRp Switches 722 and 712  5 · ΔRp Switches 722 and 713  6 · ΔRp Switches 723 and 711  7 · ΔRp Switches 723 and 712  8 · ΔRp Switches 723 and 713  9 · ΔRp Switches 724 and 711 10 · ΔRp Switches 724 and 712 11 · ΔRp Switches 724 and 713 12 · ΔRp Switches 725 and 711 13 · ΔRp Switches 725 and 712 14 · ΔRp Switches 725 and 713 15 · ΔRp Switches 726 and 711

[0056] It may be appreciated that second network 720 may comprise a series resistor network as shown in FIG. 5. It may be further appreciated that first network 710 may comprise a series network as shown in FIG. 5 as well, regardless of whether second network 720 comprises a parallel resistor network or a series resistor network. (Thus, there are four possible combinations for networks 710 and 720: parallel-parallel, series-parallel, parallel-series, and series-series).

[0057] A corresponding embodiment for the first variable resistance network 20 comprises the mirror image of embodiment 740 taken along a horizontal line above embodiment 740.

[0058] While the present invention has been particularly described with respect to the illustrated embodiments, it will be appreciated that various alterations, modifications and adaptations may be made based on the present disclosure, and are intended to be within the scope of the present invention. It should be understood that, for the purposes of interpreting the claims, that the first and second resistance networks are interchangeable. While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims. 

What is claimed is:
 1. A potentiometer network comprising: a first main terminal and a second main terminal; a first variable resistance network comprising a first terminal, a second terminal, and a variable resistance value R₁ which varies between zero ohms and R_(P) ohms, the first terminal of the first variable resistance network being coupled to the first main terminal; a second variable resistance network comprising a first terminal, a second terminal, and a variable resistance value R₂ which is substantially equal to (R_(P)−R₁), the first terminal of the second variable resistance network being coupled to the second main terminal; a resistor stack comprising a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes, each internal node coupling two adjacent resistors of the stack, the first resistor in the stack having a terminal coupled to the second terminal of the first variable resistance network, the last resistor in the stack having a terminal coupled to the second terminal of the second variable resistance network, each resistor having a value substantially equal to R_(S) ohms; a wiper terminal coupled to one of the plurality of internal nodes of the resistor stack, or to one of the second terminals of the variable resistor networks, or to one of the first and second main terminals.
 2. The potentiometer network of claim 1 wherein R_(P) has a value between 0.75·R_(S) and 1.25·R_(S).
 3. The potentiometer network of claim 1 wherein R_(P) has a value between 0.75·R_(S) and R_(S).
 4. The potentiometer network of claim 1 further comprising a wiper selection circuit, said circuit having a first selection switch coupled between the wiper terminal and the second terminal of the first variable resistance network, a second selection switch coupled between the wiper terminal and the second terminal of the second variable resistance network, and a plurality M−1 additional selection switches, each additional selection switch being coupled between the wiper terminal and a respective internal node of the resistor stack, not more than one selection switch being conductive at a time.
 5. The potentiometer network of claim 4 wherein said wiper selection circuit further comprises an additional selection switch coupled between said wiper terminal and said first main terminal, and another additional selection switch coupled between said wiper terminal and said second main terminal.
 6. The potentiometer network of claim 5 wherein each selection switch comprises a transistor.
 7. The potentiometer network of claim 5 wherein each selection switch comprises an NMOS transistor having a gate, a drain and a source, and a PMOS transistor having a gate, a drain, and a source, wherein the drain of the PMOS transistor is coupled to the drain of the NMOS transistor with the drains thereby providing a first conduction terminal of the selection switch, wherein the source of the PMOS transistor is coupled to the source of the NMOS transistor with the sources providing a second conduction terminal of the selection switch, and wherein the NMOS and PMOS transistors are driven by complementary logic signals at their gates.
 8. The potentiometer network of claim 1 wherein said first variable resistance network comprises a plurality N of discrete resistance values (n=1 to n=N) which are spaced substantially equally from one another by an increment ΔR_(P) such that each n-th value is within ½·ΔR_(P) of the quantity (n−1)·ΔR_(P), wherein ΔR_(P)=R_(P)/(N−1).
 9. The potentiometer network of claim 8 wherein each n-th value is within 0.1·ΔR_(P) of the quantity (n−1)·ΔR_(P) for at least n=2 through n=N.
 10. The potentiometer network of claim 8 wherein R_(P) is within ½·ΔR_(P) of the quantity R_(S)−ΔR_(P).
 11. The potentiometer network of claim 8 wherein R_(P) is within ¼·ΔR_(P) of the quantity R_(S)−ΔR_(P).
 12. The potentiometer network of claim 8 wherein each resistor of said resistor stack has a value that is within ½·ΔR_(P) of R_(S).
 13. The potentiometer network of claim 1 wherein each resistor of said resistor stack has a value that is within 0.1·R_(S) of R_(S).
 14. The potentiometer network of claim 8 wherein said first variable resistance network further comprises: a plurality N of selectable parallel current branches, each branch being coupled between the first and second terminals of said first variable resistance network, a first one of the current branches comprising a switch, each of the N−1 remaining current branches comprising a switch coupled in series with a resistor.
 15. The potentiometer network of claim 14 wherein the resistors of said N−1 remaining current branches have values that are within ½·ΔR_(P) of the quantities of (k−1)·ΔR_(P) for k=1 to k=N−1.
 16. The potentiometer network of claim 14 wherein the switches in the N−1 remaining current branches collectively have an average conduction resistance R_(ON) when in their conduction states, and wherein the resistors of said N−1 remaining current branches have values that are within ½·ΔR_(P) of the quantities of [(k−1)·ΔR_(P)−R_(ON)] for k=1 to k=N−1.
 17. The potentiometer network of claim 14 wherein each selection switch comprises an NMOS transistor having a gate, a drain and a source, and a PMOS transistor having a gate, a drain, and a source, wherein the drain of the PMOS transistor is coupled to the drain of the NMOS transistor with the drains thereby providing a first conduction terminal of the selection switch, wherein the source of the PMOS transistor is coupled to the source of the NMOS transistor with the sources providing a second conduction terminal of the selection switch, and wherein the NMOS and PMOS transistors are driven by complementary logic signals at their gates.
 18. The potentiometer network of claim 14 wherein each selection switch comprises one of an NMOS transistor or a PMOS transistor.
 19. The potentiometer network of claim 8 wherein said first variable resistance network further comprises: a sense terminal; and a plurality N of selectable parallel current branches, each branch being coupled between the first and second terminals of said variable resistance network, a first one of the current branches comprising a switch, each of the N−1 remaining current branches comprising a resistor and a double-pole single-throw switch, each branch's resistor being coupled in series with the first pole of the corresponding switch to form a series combination that is coupled between the first and second terminals of the first variable resistance network, each branch's resistor further being coupled in series with the second pole of the corresponding switch to form a series combination that is coupled between the first terminal and the sense terminal of the first variable resistance network; and wherein said wiper terminal is selectively coupled to the sense terminal.
 20. The potentiometer network of claim 19 wherein the resistors of said N−1 remaining current branches have values that are within ½·ΔR_(P) of the quantities of (k−1)·ΔR_(P) for k=1 to k=N−1.
 21. The potentiometer network of claim 19 wherein each selection switch comprises an NMOS transistor having a gate, a drain and a source, and a PMOS transistor having a gate, a drain, and a source, wherein the drain of the PMOS transistor is coupled to the drain of the NMOS transistor with the drains thereby providing a first conduction terminal of the selection switch, wherein the source of the PMOS transistor is coupled to the source of the NMOS transistor with the sources providing a second conduction terminal of the selection switch, and wherein the NMOS and PMOS transistors are driven by complementary logic signals at their gates.
 22. The potentiometer network of claim 19 wherein each selection switch comprises one of an NMOS transistor or a PMOS transistor.
 23. The potentiometer network of claim 8 wherein said first variable resistance network further comprises: a plurality N−1 of resistors coupled in series at a set of N−2 intermediate nodes to form a line of series-connected resistors, the first and last resistors each having a free terminal which is not connected to an intermediate node, the free terminal of the first resistor in the line being coupled to the first terminal of said first variable resistance network; and a plurality N of switches, a first one of the switches being coupled between the first and second terminals of the first variable resistance network, a second one of the switches being coupled between the free terminal of the last resistor in the line and the second terminal of the first variable resistance network, and each of the remaining ones of said switches being coupled between a respective intermediate node and the second terminal of the first variable resistance network.
 24. The potentiometer network of claim 23 wherein each of said resistors has a value within ½·ΔR_(P) of ΔR_(P).
 25. The potentiometer network of claim 24 wherein the switches have an average conduction resistance RON when in their conduction states, and wherein the first resistor has a value that is within ½·ΔR_(P) of the quantity (ΔR_(P)−R_(ON)).
 26. The potentiometer network of claim 23 wherein each selection switch comprises an NMOS transistor having a gate, a drain and a source, and a PMOS transistor having a gate, a drain, and a source, wherein the drain of the PMOS transistor is coupled to the drain of the NMOS transistor with the drains thereby providing a first conduction terminal of the selection switch, wherein the source of the PMOS transistor is coupled to the source of the NMOS transistor with the sources providing a second conduction terminal of the selection switch, and wherein the NMOS and PMOS transistors are driven by complementary logic signals at their gates.
 27. The potentiometer network of claim 23 wherein each selection switch comprises one of an NMOS transistor or a PMOS transistor.
 28. The potentiometer network of claim 8 wherein said first variable resistance network further comprises: a sense terminal; a plurality N−1 of resistors coupled in series at a set of N−2 intermediate nodes to form a line of series-connected resistors, the first and last resistors each having a free terminal which is not connected to an intermediate node, the free terminal of the first resistor in the line being coupled to the first terminal of said variable resistance network; a first switch coupled between the first and second terminals of the first variable resistance network; and a plurality N−1 of double-pole single-throw switches, a first one of the switches having its first pole coupled between the free terminal of the last resistor in the line and the second terminal of the first variable resistance network and having its second pole coupled between the free terminal of the last resistor in the line and the sense terminal, each remaining double-pole switch having its first pole coupled between a respective intermediate node and the second terminal of the first variable resistance network and having its second pole coupled between the same respective intermediate node and the sense terminal.
 29. The potentiometer network of claim 28 wherein each of said resistors has a value within ½·ΔR_(P) of ΔR_(P).
 30. The potentiometer network of claim 28 wherein each selection switch comprises an NMOS transistor having a gate, a drain and a source, and a PMOS transistor having a gate, a drain, and a source, wherein the drain of the PMOS transistor is coupled to the drain of the NMOS transistor with the drains thereby providing a first conduction terminal of the selection switch, wherein the source of the PMOS transistor is coupled to the source of the NMOS transistor with the sources providing a second conduction terminal of the selection switch, and wherein the NMOS and PMOS transistors are driven by complementary logic signals at their gates.
 31. The potentiometer network of claim 28 wherein each selection switch comprises one of an NMOS transistor or a PMOS transistor.
 32. The potentiometer network of claim 8 wherein said first variable resistance network further comprises: a first resistor network having a first terminal coupled to the first terminal of said first variable resistance network, a second terminal coupled to an intermediate node, and two or more switches and one or more resistors configured to provide a selectable resistance between the first and second terminals of the first resistor network; and a second resistor network having a first terminal coupled to the intermediate node, a second terminal coupled to the second terminal of said first variable resistance network, and two or more switches and one or more resistors configured to provide a selectable resistance between the first and second terminals of the second resistor network.
 33. The potentiometer network of claim 32 wherein said first variable resistance network further comprises a sense terminal; and wherein said second resistor network comprises a plurality X of selectable parallel current branches, each branch being coupled between the first and second terminals of the second resistor network, a first one of the current branches comprising a switch, each of the X−1 remaining current branches comprising a resistor and a double-pole single-throw switch, each branch's resistor being coupled in series with the first pole of the corresponding switch to form a series combination that is coupled between the first and second terminals of the second resistor network, each branch's resistor further being coupled in series with the second pole of the corresponding switch to form a series combination that is coupled between the first terminal of the second resistor network and sense terminal of the first variable resistance network; and wherein said wiper terminal is selectively coupled to said sense terminal.
 34. The potentiometer network of claim 33 wherein said first resistor network comprises a plurality Y of selectable parallel current branches, each branch being coupled between the first and second terminals of the first resistor network, a first one of the current branches comprising a switch, each of the Y−1 remaining current branches comprising a resistor coupled in series with a switch to form a series combination that is coupled between the first and second terminals of the first resistor network.
 35. The potentiometer network of claim 1 wherein said second variable resistance network comprises a plurality N of discrete resistance values, n=1 to n=N, which are spaced substantially equally from one another by an increment ΔR_(P) such that each n-th value is within ½·ΔR_(P) of the quantity (n−1)·ΔR_(P), wherein ΔR_(P)=R_(P)/(N−1).
 36. A variable resistance network comprising: a first terminal and a second terminal between which a variable resistance is provided; a sense terminal; and a plurality N of selectable parallel current branches, each branch being coupled between the first and second terminals of said variable resistance network, a first one of the current branches comprising a switch, each of the N−1 remaining current branches comprising a resistor and a double-pole single-throw switch, each branch's resistor being coupled in series with the first pole of the corresponding switch to form a series combination that is coupled between the first and second terminals of the variable resistance network, each branch's resistor further being coupled in series with the second pole of the corresponding switch to form a series combination that is coupled between the first terminal and sense terminal of the variable resistance network.
 37. The variable resistance network of claim 36 wherein said network has a plurality N of discrete resistance values, n=1 to n=N, which are spaced substantially equally from one another by an increment ΔR_(P) such that each n-th value is within ½·ΔR_(P) of the quantity (n−1)·ΔR_(P), wherein ΔR_(P)=R_(P)/(N−1), and wherein the resistors of said N−1 remaining current branches have values that are within ½·ΔR_(P) of the quantities of (k−1)·ΔR_(P) for k=1 to k=N−1.
 38. A variable resistance network comprising: a first terminal and a second terminal between which a variable resistance is provided; a sense terminal; a plurality N−1 of resistors coupled in series at a set of N−2 intermediate nodes to form a line of series-connected resistors, the first and last resistors each having a free terminal which is not connected to an intermediate node, the free terminal of the first resistor in the line being coupled to the first terminal of the variable resistance network; a first switch coupled between the first and second terminals of the variable resistance network; and a plurality N−1 of double-pole single-throw switches, a first one of the switches having its first pole coupled between the free terminal of the last resistor in the line and the second terminal of the variable resistance network and having its second pole coupled between the free terminal of the last resistor in the line and the sense terminal, each remaining double-pole switch having its first pole coupled between a respective intermediate node and the second terminal of the variable resistance network and having its second pole coupled between the same respective intermediate node and the sense terminal.
 39. The variable resistance network of claim 38 wherein said network has a plurality N of discrete resistance values, n=1 to n=N, which are spaced substantially equally from one another by an increment ΔR_(P) such that each n-th value is within ½·ΔR_(P) of the quantity (n−1)·ΔR_(P), wherein ΔR_(P)=R_(P)/(N−1), and wherein each of said resistors has a value within ½·ΔR_(P) of ΔR_(P).
 40. A method of adjusting the wiper position of a potentiometer which has a first main terminal, a second main terminal, a wiper terminal, a first variable resistor, a second variable resistor, and a resistor stack, said resistor stack having a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes, each internal node coupling two adjacent resistors of the stack, the first resistor in the stack having a terminal at the first end of the resistor stack and the last resistor in the stack having a terminal at the second end of the resistor stack, the first variable resistor having a first terminal coupled to the potentiometer's first main terminal and a second terminal coupled to the first end of the resistor stack, and the second variable resistor having a first terminal coupled to the potentiometer's second main terminal and a second terminal coupled to the second end of the resistor stack, said method comprising the steps of: (a) adjusting the wiper terminal to a coarse resolution by selectively coupling the wiper terminal to one of the internal nodes of the resistor stack or to one of the ends of the resistor stack; and (b) adjusting the wiper terminal to a finer resolution by varying the value of at least one of the variable resistors, each variable resistor being coupled to a respective end of the resistor stack.
 41. The method of claim 40 wherein the first variable resistor has a resistance value R₁, wherein the second variable resistor has a resistance value R₂, and wherein step (b) comprises the step of adjusting the first and second resistors in a complementary manner such that the total of resistance values R₁ and R₂ is substantially a constant. 